As for the consumer electronics products within the developing process, sonic indicators or parameters cannot be completely determined in advance. For example, some soft codes need to be constantly adjusted and changed according to the test result, and they will be determined until the design requirement is met. Accordingly, during the development of this type of chip, an OTP (One Time Programmable) memory is inevitably used. The storage data of the memory cell of the OTP memory is initialized to be “1”, which can be written to be “0” by programming according the demand, such that the code can be easily adjusted and changed.
The memory cell of the common logic OTP is composed of two PMOS transistors connected in series, its initial physical implementation is shown in FIG. 1, in which the source of the second TWOS transistor is connected to a source line, the gate is floating and electrically neutralized; the drain is connected to the source of the first PMOS transistor, while the gate of the first PMOS transistor is connected to a strobe terminal, the drain is connected to a bit line, such that the storage data of the memory cell is “1”. During the process of programming, a high programming voltage is applied to the drain and the gate of the first PMOS transistor, and the source of the second PMOS transistor is connected to ground. A large number of electrons flow from the source to the drain, thus forming a fairly large current and a large amount of hot electrons. Due to the greater concentration, some electrons reach the silicon dioxide layer between the substrate and the floating gate. Since the gate of the first PMOS transistor is applied with high voltage, the electrons can reach the floating gate through the silicon dioxide layer under the electrical field and form an electron group on the floating gate. The electron group remains on the floating gate even in case of power failure, such that the information can be retained for a long time, thus the writing of “0” is completed, which is shown in FIG. 2. Since the second PMOS transistor with electron on the gate is normally on, during the reading process, there is current flowing between the two PMOS transistors by biasing of the terminal, while the PMOS transistor without electron on the gate is normally off, during the reading process, there is current flowing between the two PMOS transistors. Accordingly, the data can be read by determining the current.
During the process of developing the chip, due to the feature of this type of memory, the test time is very long, and the test cost is very high, which will greatly increase chip production cycle, thus greatly reducing the profit of products after mass production.